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page 1 of 15 www.irf.com 12/22/2007 data sheet no. pd60322 i p2004 features ? 40a multiphase building block ? no derating up to t c = t pcb = 95oc ? optimized for low power loss ? bias supply range of 4.5v to 6.0v ? operation up to 1.5mhz ? over temperature protection ? bi-directional current flow ? under voltage lockout ? lga interface ? 7.7mm x 7.7mm x 2.2mm package applications ? high frequency, multi-phase converters ? low duty-ratio, high current microprocessor power supplies ? high frequency low profile dc-dc converters synchronous buck lga power block description the IP2004 is a fully optimized solution for high current synchronous buck multiphase applications. board space and design time are greatly reduced be cause most of the components required for each phase of a typical discrete-based multiphase circuit are integrated into a single 7.7mm x 7.7mm x 2.2mm power block. the only additional components required for a complete multiphase converter are a pwm controller, the output inductors, and the input and output capacitors. package description interface connection standard quantity t & r orientation IP2004 lga 10 n/a IP2004tr lga 2000 figure 18 typical application v in v sw p gnd p gnd nc pwm enable v dd i p2004 v in v out vo3 ph_en1 pwm1 ph_en2 pwm2 5v_sns v cc v in ocset1 v sw 1 ocset1 v sw 2 v sw 1 v sw 2 gnd ss2 ss1 pgood2 pgood1 comp2 comp1 rt track2 track1 sync seq enable vp2 fb2 fb2 vp2 vp1 vref fb1 vp2 fb2 v out v sws1 v sws2 v in v sw p gnd p gnd pwm enable v dd i p2004 nc v sws1 v sws2 ir3623
page 2 of 15 www.irf.com 12/22/2007 data sheet no. pd60322 i p2004 absolute maximum ratings v in to pgnd ????????..??.?. -0.5v to 16v v dd to pgnd ????????.?.??. -0.5v to 6.5v pwm to pgnd ???????.???? -0.5v to v dd + 0.5v (note 1) enable to pgnd ?????????... -0.5v to v dd + 0.5v (note 1) storage temperature ????. .????. -60oc to 150oc block temperature ????...????? -40oc to 150oc (note 5) esd rating??????????.???. hbm class 1b (500v) mm class b (200v) msl rating??????????.???. 3 caution: stresses above those listed in ?a bsolute maximum ratings? may cause permanent damage to the device. this is a stress only rating and operation of the device at these or any other conditions above those listed in the ?recommended operating conditions? section of this specification is not implied. recommended operating conditions parameter min typ max units conditions supply voltage (v dd ) 4.5 - 6.0 v input voltage (v in ) 3.3 - 13.2 v output voltage (v out ) - - 8.0 v output current (i out ) - - 40 a switching frequency (f sw ) 250 - 1500 khz on time duty cycle - - 85 % minimum v sw on time 60 - - ns v dd = 5.0v, v in = 12v block temperature -40 - 125 oc electrical specifications these specifications apply for t blk = 0oc to 125oc and v dd = 5.0v, unless otherwise specified. parameter min typ max units conditions ploss power block losses - 7.4 9.1 w v in = 12v, v dd = 5.0v, v out = 1.3v, i out = 40a, f sw = 1mhz, l out = 0.3uh, t a = 25oc (note 3) v in quiescent current - - 1.0 ma v in = 12v, enable = 0v
page 3 of 15 www.irf.com 12/22/2007 data sheet no. pd60322 i p2004 parameter min typ max units conditions vdd supply current (stand by) - 1.1 2.0 ma v dd = 5.0v, enable = 0v supply current (operating) - 70 110 ma v in = 12v, v dd = en able = 5.0v, f sw = 1mhz, 10% dc, power-on reset (por) vcc rising 3.7 - 4.5 v hysterisis 140 185 230 mv v i rising & falling enable input logic level low threshold (v il ) - - 0.8 v schmitt trigger input vcc = por to 6.0v logic level high threshold (v ih ) 2.0 - - v threshold hysterisis - 100 - mv weak pull-down current - 10 - a rising propagation delay (t pdh ) - 40 - ns falling propagation delay (t pdl ) - 75 - ns pwm input logic level low threshold (v il ) - - 0.8 v schmitt trigger input vcc = por to 6.0v (note 4) logic level high threshold (v ih ) 2.0 - - v threshold hysterisis - 100 - mv weak pull-down current - 2 - a rising propagation delay (t pdh ) - 50 - ns falling propagation delay (t pdl ) - 35 - ns notes: 1. must not exceed 6.5v. 2. guaranteed by design, not tested in production. 3. measurement made with six 10f (tdk c3225x5r1c1 06kt or equivalent) ceramic capacitors across v in to p gnd pins (see figure 9). 4. tpdh and tpdl are not associated with rise and fall times. does not affect power loss (see figure 10). 5. block temperature is defined as an y die temperature within the package.
page 4 of 15 www.irf.com 12/22/2007 data sheet no. pd60322 i p2004 power loss curve 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 power loss(w) output current(a) typical maximum v i = 12v v d = 5.0v v o = 1.3v f sw = 1mhz l o = 300nh t blk = 125oc figure 1power loss versus output current soa curve 0 4 8 12 16 20 24 28 32 36 40 44 0 102030405060708090100110120130 output current (a) pcb temperature (oc) tx 0 10 20 30 40 50 60 70 80 90 10 0 110 120 130 case temperature (oc) v i = 12v v d = 5.0v v o = 1.3v f sw = 1mhz l o = 300nh safe operating area figure 2 safe operating area (soa) versus pcb and case temperatures (see page 6 for details)
page 5 of 15 www.irf.com 12/22/2007 data sheet no. pd60322 i p2004 typical performance curves -2.4 -1.2 0.0 1.2 2.4 3.6 4.8 6.0 7.2 8.4 9.6 0.90 0.95 1.00 1.05 1.10 1.15 1.20 1.25 1.30 1.35 1.40 345678910111213 soa temp adjustment (oc) power loss (normalized) input voltage (v) v d = 5.0v v o = 1.3v i o = 40a f sw = 1mhz l o = 300nh t blk = 125oc figure 3 normalized power loss vs. input voltage -2.4 -1.2 0.0 1.2 2.4 3.5 4.7 5.9 7.1 0.90 0.95 1.00 1.05 1.10 1.15 1.20 1.25 1.30 0.8 1.1 1.3 1.6 1.8 2.1 2.3 2.6 2.8 3.1 3.3 soa temp adjustment (oc) power loss (normalized) output voltage (v) ` v i = 12.0v v dd = 5.0v i out = 40a f sw = 1mhz l o = 300nh t blk = 125oc figure 4 normalized power loss vs. output voltage -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 0.92 0.94 0.96 0.98 1.00 1.02 1.04 1.06 4.50 4.75 5.00 5.25 5.50 5.75 6.00 soa temperature adjustment (oc) power loss (normalized) drive voltage (v) v i = 12.0v v o = 1.3v i o = 40a f sw = 1mhz l o = 300nh t blk = 125oc figure 5 normalized power loss versus drive voltage -0.9 -0.5 0.0 0.5 0.9 1.4 1.9 2.4 2.8 0.96 0.98 1.00 1.02 1.04 1.06 1.08 1.10 1.12 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 soa temp adjustment (oc) power loss (normalized) output inductor (h) v i = 12.0v v dd = 5.0v v o = 1.3v i out = 40a f sw = 1mhz t blk = 125oc figure 6 normalized power loss vs. inductance -7.1 -5.9 -4.7 -3.6 -2.4 -1.2 0.0 1.2 2.4 3.5 4.7 5.9 7.1 0.70 0.75 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 1.25 1.30 250 375 500 625 750 875 1000 1125 1250 1375 1500 soa temp adjustment (oc) power loss (normalized) switching frequency (khz) v i = 12.0v v dd = 5.0v v o = 1.3v i out = 40a l o = 300nh t blk = 125oc figure 7 normalized power loss vs. switching frequency 10 20 30 40 50 60 70 80 90 100 110 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 average supply current (ma) switching frequency (khz) v i = 12.0v v dd = 5.0v v o = 1.3v i out = 40a l o = 300nh t blk = 125oc figure 8 v dd supply current vs. frequency
page 6 of 15 www.irf.com 12/22/2007 data sheet no. pd60322 i p2004 a dc v average input voltage average input current p in = v in average x i in average p dd = v dd average x i dd average p out = v out average x i out average p loss = (p in + p dd ) - p out dc v average vdd voltage a average vdd current i p2004 v in v sw p gnd p gnd nc pwm enable v dd v sws1 a average output current averaging circuit v average output voltage v sws2 figure 9 power loss test circuit t pdh t pdl pwm v sw 90% 10% 90% 10% figure 10 timing diagram applying the safe operating area (soa) curve the soa graph incorporates power loss and the rmal resistance information in a way that allows one to solve for maximum current capabi lity in a simplified graphical manner. it incorporates the ability to solve thermal problem s where heat is drawn out through the printed circuit board and the top of the case. please refe r to international rectifier application note an1047 for further details on using this soa curve in your thermal environment. procedure 1. calculate (based on estimated power loss) or measure the case temperature on the device and the board temper ature near the device (1mm from the edge). 2. draw a line from case temperatur e axis to the pcb temperature axis. 3. draw a vertical line from the t x axis intercept to the soa curve. 4. draw a horizontal line from the intersecti on of the vertical line with the soa curve to the y-axis (output current). the point at which the horizont al line meets the y-axis is the soa continuous current. 0 4 8 12 16 20 24 28 32 36 40 44 0 10 20 30 40 50 60 70 80 90 100 110 120 130 pcb temperature (oc) output current (a) tx 0 10 20 30 40 50 60 70 80 90 100 110 120 130 case temperature (oc) v i = 12v v d = 5.0v v o = 1.3v f sw = 1mhz l o = 300nh safe operating area figure 11 soa example, continuous current 30a for t pcb = 95oc & t case = 110oc
page 7 of 15 www.irf.com 12/22/2007 data sheet no. pd60322 i p2004 calculating power loss and soa for different operating conditions to calculate power loss for a given set of operation conditions, t he following procedure should be followed: power loss procedure 1. determine the maximum current for eac h IP2004 and obtain the maximum power loss from figure 1 2. use the normalized curves in page 5 to obt ain power loss values that match the operating conditions in the application 3. the maximum power loss under the applicat ion conditions is then the product of the power loss from figure 1 and the normalized values. to calculate the safe operating area (soa) for a given set of operating conditions, the following procedure should be followed: soa procedure 1. determine the maximum pcb and case temperature at t he maximum operating current for each IP2004 2. use the normalized curves in page 5 to obtain soa temperatur e adjustments that match the operating conditi ons in the application 3. then, add the sum of the soa temperature adjus tments to the t x axis intercept in figure 2 design example operating conditions: output current = 30a input volt age = 10v output voltage = 3.3v switching freq = 750khz inducto r = 0.2h drive voltage (v dd ) = 5.5v calculating maximum power loss: (figure 1) maximum power loss = 8.0w (figure 3) normalized power loss for input voltage 0.98 (figure 4) normalized power loss for output voltage 1.23 (figure 5) normalized power loss for drive voltage (v dd ) 0.96 (figure 6) normalized power loss for output inductor 1.03 (figure 7) normalized pow er loss for switch frequency 0.91 calculated maximum power loss 8.0w x 0.98 x 1.23 x 0.96 x 1.03 x 0.91 8.68w
page 8 of 15 www.irf.com 12/22/2007 data sheet no. pd60322 i p2004 calculating soa temperature: (figure 3) soa temperatur e adjustment for input voltage -0.5oc (figure 4) soa temperatur e adjustment for output voltage 5.5oc (figure 5) soa temperatur e adjustment for drive voltage (v dd ) -0.8 oc (figure 6) soa temperatur e adjustment for output inductor 0.6 oc (figure 7) soa temperature adjustment for switch frequency -1.9 oc tx axis intercept adjustment -0.5 oc + 5.5 oc - 0. 8 oc + 0.6 oc - 1.9 oc 2.9 oc assuming t pcb = 95oc & t case = 110oc the following example shows how t he soa current is adjusted for t x increase of 2.9oc 0 4 8 12 16 20 24 28 32 36 40 44 0 102030405060708090100110120130 pcb temperature (oc) output current (a) tx 0 10 20 30 40 50 60 70 80 90 100 110 120 130 case temperature (oc) v i = 12v v d = 5.0v v o = 1.3v f sw = 1mhz l o = 300nh safe operating area 1. draw a line from case temperatur e axis to the pcb temperature axis. 2. draw a vertical line from the t x axis intercept to the soa curve. 3. draw a horizontal line from the intersecti on of the vertical line with the soa curve to the y-axis (output current). the point at which the horizont al line meets the y-axis is the soa continuous current. 4. draw a new vertic al line from the t x axis by adding or subtracting the soa adjustment temperature from the original t x intercept point. 5. draw a horizontal line from the intersecti on of the new vertical line with the soa curve to the y-axis (output current). the point at which the hor izontal line meets the y-axis is the new soa continuous current. the soa adjustment indicates the part is still a llowed to run at a cont inuous current of 30a.
page 9 of 15 www.irf.com 12/22/2007 data sheet no. pd60322 i p2004 internal block diagram mosfet driver with dead time control v in v sw p gnd v dd pwm enable nc v sws1 v sws2 1 2 6 3 4 5 7 89 p gnd 10 figure 12 internal block diagram pin description pin number pin name description 1 nc no connect. this pin is not for electrical connection 2 enable when set to logic level high, internal circuitry of the device is enabled. when set to logic level low, the control and synchronous fets are turned off. 3 pwm ttl level input to mosfet drivers. when pwm is high, the control fet is on and the sync fet is off. when pwm is low, the sync fet is on and the control fet is off. 4 v dd supply voltage to internal circuitry. 5 v sw voltage switching node ? pin conn ection to the output inductor. 6, 10 pgnd power ground 7 v in input voltage pin. connect inpu t capacitors close to this pin. 8 v sws1 floating pin. externally connect to v sws2 only. 9 v sws2 floating pin. externally short to v sws1 only.
page 10 of 15 www.irf.com 12/22/2007 data sheet no. pd60322 i p2004 package pinout diagram nc 1 enable 2 pwm 3 v dd 4 v sws1 8 v sws2 9 p gnd 10 v in 7 p gnd 6 v sw 5 figure 13 top side transparent view
page 11 of 15 www.irf.com 12/22/2007 data sheet no. pd60322 i p2004 recommended pcb layout figure 14 top copper and solder- mask layer of pcb layout
page 12 of 15 www.irf.com 12/22/2007 data sheet no. pd60322 i p2004 figure 15 top & bottom component and via placement (topside, tran sparent view down) pcb layout guidelines the following guidelines are recommended to reduce the parasitic values and optimize overall performance. ? all pads on the IP2004 footprint design need to be solder-mask defined (see figure 14 ). also refer to international rectifier application notes an1028 and an1029 for further footprint design guidance. ? place as many vias around the power pads (v in , v sw , and p gnd ) for both electrical and optimal thermal performance. o vias in between the different power pads may overlap the pad opening and solder mask edge without the need to plug the via hole. vias with a 13mil drill hole and 25mil capture pad were used in this example. ? a minimum of six 10f, x5r, 16v ceramic capa citors per IP2004 are needed for greater than 25a operation. this will result in the lo west loss due to input capacitor esr. ? placement of the ceramic input capacitors is critic al to optimize switching performance. in cases where there is a heatsink on the case of IP2004, place all six ceramic capacitors right underneath the IP2004 footprint (see bottom component layer). in case s where there is not heatsink, c1 and c6 on the bottom layer may be moved to the c1x and c6x locati ons (respectively) on the top component layer (see top component layer). in both cases, c2 ? c5 need to be placed right underneath the IP2004 pcb footprint. ? dedicate at least two layer to for pgnd only ? duplicate the power nodes on multiple layers (refer to an1029).
page 13 of 15 www.irf.com 12/22/2007 data sheet no. pd60322 i p2004 mechanical outline drawing 0.07 [.0027] c 2. dimensions are shown in millimeters [inches]. 3. controlling dimension: millimeter 1. dimensioning & tolerancing per asme y14.5m-1994. notes: top view bottom view side view c solder resist opening 4 primary datum c (seating plane) is defined by the 4 0.15 [.006] c corner id b a 0.15 [.006] c 2.21 [.087] corner id 7x 1.016 7.65 [0.301] 7.65 [0.301] 0.322 4.132 4.779 5.795 7.319 0.334 1.858 2.379 5.300 5.821 7.345 6.303 6.583 3.865 2.54 5.021 3.459 2.010 6x 0.762 5. drawing not to scale. bottom view electrical i/o 1 nc 2 enable 3 pwm 4 v dd 5 v sw 6 p gnd 7 v in 8 v sws1 9 v sws2 10 p gnd figure 16 mechanical outline drawing
page 14 of 15 www.irf.com 12/22/2007 data sheet no. pd60322 i p2004 recommended solder paste stencil design figure 17 solder paste stencil design tape and reel information figure 18 tape & reel information
page 15 of 15 www.irf.com 12/22/2007 data sheet no. pd60322 i p2004 part marking figure 19 part marking data and specifications subject to change without notice. ir world headquarters: 233 kansas st., el segundo, californi a 90245, usa tel: (310) 252-7105 tac fax: (310) 252-7903 visit us at www.irf.com for sales contact information

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